The following figure shows the block diagram of the Cyclone® IV GX FPGA transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on your requirements. Diagnostic features such as serial loopback, parallel loopback, reverse serial loopback, and loopback master and slave capability in the PCI-SIG* compliant PCI Express* hard IP block.On-chip power supply decoupling to satisfy transient current requirements at higher frequencies, which reduces the need for on-board decoupling capacitors.On-die power supply regulators for transmitter and receiver PLL charge pump and voltage controlled oscillator (VCO) for superior noise immunity.8B/10B encoder and decoder that performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding.Built-in byte ordering so that a frame or packet always starts in a known byte lane.Two phase-locked loop (PLL) inputs on each transmitter the EP4CGX50 device and larger devices also have independent clock dividers to allow different clock rates for each channel.2) If the voltage on pin 2 is more negative than -3 Volts, then it is a DTE, otherwise it should be near zero volts. Be sure the black lead is connected to pin 7 (Signal Ground) and the red lead to whichever pin you are measuring. PIPE interface that connects directly to embedded PCI Express* Gen1 (2.5 Gbps) hard intellectual property (IP) to support PCI-SIG* compliant x1, x2, or x4. 1 ) Measure the DC voltages between (DB25) pins 2 & 7 and between pins 3 & 7.Dedicated circuitry compliant with the physical interface for PCI Express*, XAUI, and Gbps Ethernet.Support for protocol features such as spread-spectrum clocking in PCI Express*, DisplayPort, V-by-One, and SATA configurations.Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel without reprogramming the FPGA.User-controlled receiver equalization to compensate for frequency-dependent losses in the physical medium.Programmable pre-emphasis settings and adjustable differential output voltage (VOD) for improved signal integrity.Flexible and easy-to-configure transceiver datapath to implement industry-standard and proprietary protocols.Up to eight transceivers with clock data recovery (CDR), supporting data rates from 600 Mbps to 3.125 Gbps.This flexibility helps you fully utilize all available transceiver resources and keep designs in a smaller and lower cost device. The Cyclone® IV GX FPGA was specifically designed to allow the implementation of multiple protocols in a single quad and to allow independent receive and transmit frequencies. Not all low-cost transceivers are created equally. The Cyclone® IV FPGA family extends the Intel® Cyclone® FPGA series leadership in providing the market’s lowest cost, lowest power FPGAs, now with transceivers. Cyclone® IV GX FPGAs: Transceiver Overview
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